1. Field of the Invention
The present invention relates to a differential minimum shift keying (DMSK) demodulator. More specifically, the invention relates to a DMSK demodulator having non-redundant double error correction capability.
2. Description of Related Art
Minimum-shift keying (MSK) signals have been widely applied to nonlinear and power limited communication systems such as satellite communication systems, mobile communication systems, IFF communication systems, and others. The widespread use of MSK is due to a significant property of MSK signals that the envelope of the signals is constant and suffers little degradation from nonlinear systems. MSK signals can be demodulated by either coherent demodulators or differential demodulators. Differential demodulators are very attractive because they require simpler circuit configurations and they do not require carrier recovery. However, the bit error rate (BER) performance for differential demodulators is inferior to that for coherent demodulators.
Non-redundant error correction demodulators have been designed to improve BER performance for DMSK signals. Unlike other demodulators that use error correcting codes such as Reed-Solomon Code, the non-redundant error correcting demodulators do not use additional redundant bits. Non-redundant error-correcting demodulators utilize the outputs of higher orders (multi-bit) of differential detectors along with the output of a conventional first order (single-bit) differential detector. The outputs of the first order differential detector provide the modulated MSK digital signals. The outputs of higher order detectors may be used as a parity check sum for the outputs of the first order detector. For instance, in the absence of errors, a bit detected by a second order differential detector is equal to modulo-2 sum of two consecutive bits detected by the first order differential detector, and a bit detected by a third order differential detector is equal to modulo-2 sum of three consecutive bits detected by the first order differential detector, and so on.
U.S. Pat. No. 4,128,828 discloses a DMSK demodulator with non-redundant single-error correcting capability that utilizes the outputs of a second order differential detector and a first order, single-bit, “conventional” differential detector. This demodulator has been shown to improve BER performance by more than 1 dB. See, e.g. T. Masamura, et al., “Differential Detection of MSK with Nonredundant Error Correction,” IEEE Trans. Communications, COM-27, June 1979; and H. Weining, “Performance Analysis and Improved Detection for DMSK with Non-redundant Error Correction,” IEEE Proceedings I, Volume 137, Issue 6, December 1990.
An additional improvement of about 0.5 dB has been gained through the use of a double-error correcting DMSK demodulator, proposed by T. Masamura, “Intersymbol Interference Reduction for Differential MSK by Nonredundant Error Correction,” IEEE Transactions on Vehicular Technology, Vol. 9, No. 1, February 1990 (hereinafter the “Masamura demodulator”). The operation of the Masamura double-error correcting demodulator is based on four stages: (i) a differential detector stage, (ii) a syndrome generator stage, (iii) a syndrome register stage, and (iv) a pattern detector stage.
In the differential detector stage, the Masamura demodulator uses three differential detectors: a first order differential detector, a second order differential detector, and a third order differential detector.
In the syndrome generator stage, the outputs of the three detectors are coupled through Exclusive-OR (XOR) gates to form a pair of syndrome values, which is delivered to the syndrome register. The register outputs to the pattern detector a syndrome pattern matrix consisting of the syndrome pair and two other syndrome pairs associated with the two preceding consecutive time intervals (bits). The pattern detector compares the syndrome pattern against nine sorted patterns to determine if there is an erroneous bit. There are 64 possible syndrome patterns that may be delivered by the syndrome register. The output of the pattern detector is added to the output of the first order differential detector delayed by two bit intervals to correct the received data. This means that at the end of the demodulation process, two bits are left without correction. Also, the output of the pattern detector must be delivered back to the syndrome register to correct for some delayed syndrome values.
The shortcomings of the Masamura double-error correcting DMSK demodulator reside in the syndrome register and in the pattern detector. In the syndrome register, a syndrome pair should ideally be used over three consecutive time intervals. This may lead to the propagation of higher order errors, despite the use of Exclusive-OR gates in the register for eliminating the single and double errors.
Moreover, in the pattern detector, a system memory is required to store the nine error patterns. Each pattern has a length of six elements (or bits). Furthermore, the process of detecting the nine error patterns from the 64 possible syndrome patterns is time consuming and may not yield accurate results. This is because those patterns are not orthogonal to the error being detected, and they do not have any other criteria characterizing them to facilitate the error detection process.
Pattern detection has been replaced with a threshold detector in a DMSK demodulator proposed by Y. Han et al., “DMSK System with Nonredundant Error Correction Capability,” IEEE GLOBECOM-91, 1991. However, this demodulator uses the outputs of a sixth order differential detector. Reliance on output of such high order detector creates more uncertainty at the outset of the demodulation process, and leaves five uncorrected bits at the end of the process rather than two.
The present invention provides a design for a double-error correcting DMSK demodulator that overcomes the shortcomings of double-error correcting DMSK demodulators such as the Masamura demodulator.